Modeling Communication in Cache-Coherent SMP Systems - A Case-Study with Xeon Phi
(In Proceedings of the 22nd international symposium on High-performance parallel and distributed computing, presented in New York City, NY, USA, pages 97--108, ACM, ISBN: 978-1-4503-1910-2, Jun. 2013)
Abstract
Most multi-core and some many-core processors implement
cache coherency protocols that heavily complicate the design
of optimal parallel algorithms. Communication is performed
implicitly by cache line transfers between cores, complicating the understanding of performance properties. We developed an intuitive performance model for cache-coherent architectures and demonstrate its use with the currently most
scalable cache-coherent many-core architecture, Intel Xeon
Phi. Using our model, we develop several optimal and optimized algorithms for complex parallel data exchanges. All
algorithms that were developed with the model beat the performance of the highly-tuned vendor-specific Intel OpenMP
and MPI libraries by up to a factor of 4.3. The model can
be simplified to satisfy the tradeoff between complexity of
algorithm design and accuracy. We expect that our model
can serve as a vehicle for advanced algorithm design, similar
to established network models such as LogP.
Documents
download article: download slides:
Recorded talk (best effort)
BibTeX
@inproceedings{ramos-hoefler-cc-modeling, author={Sabela Ramos and Torsten Hoefler}, title={{Modeling Communication in Cache-Coherent SMP Systems - A Case-Study with Xeon Phi}}, year={2013}, month={Jun.}, pages={97--108}, booktitle={Proceedings of the 22nd international symposium on High-performance parallel and distributed computing}, location={New York City, NY, USA}, publisher={ACM}, isbn={978-1-4503-1910-2}, source={http://www.unixer.de/~htor/publications/}, }
