The ubiquity of accelerators in high-performance
computing has driven programming complexity beyond the skill-set of the
average domain scientist. To maintain performance portability in the future,
it is imperative to decouple architecture-specific programming paradigms
from the underlying scientific computations.
We present the Stateful DataFlow multiGraph (SDFG), a data-centric
intermediate representation that enables separating program definition from
its optimization. By combining fine-grained data dependencies with
high-level control-flow, SDFGs are both expressive and amenable to
high-level program transformations, such as tiling and double-buffering.
These transformations are applied to the SDFG in an interactive process,
using extensible pattern matching, graph rewriting, and a graphical user
interface. We demonstrate SDFGs on CPUs, GPUs, and FPGAs over various
motifs --- from fundamental computational kernels to graph analytics. We
show that SDFGs deliver competitive performance, allowing domain scientists
to develop applications naturally and port them to approach peak hardware
performance without modifying the original scientific code.
@inproceedings{, author={Tal Ben-Nun and Johannes de Fine Licht and Alexandros Nikolaos Ziogas and Timo Schneider and Torsten Hoefler}, title={{Stateful Dataflow Multigraphs: A Data-Centric Model for Performance Portability on Heterogeneous Architectures}}, year={2019}, month={Nov.}, booktitle={Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis (SC19)}, source={http://www.unixer.de/~htor/publications/}, }
